Stacked semiconductor package

ABSTRACT

A stacked semiconductor package comprises two semiconductor chips ( 11, 12 ) each of which has a mounting surface provided with a plurality of chip pins arranged in a predetermined pattern. The semiconductor chips are mounted on opposite surfaces of a substrate ( 13 ) so that the mounting surfaces are faced to each other through the substrate. The substrate is provided with a plurality of package pins formed in an area other than a chip mounting area and arranged in a pattern identical to the predetermined pattern. A pair of the corresponding chip pins of the semiconductor chips are connected to a via formed at an intermediate position therebetween by the use of branch wires equal in length to each other. The via is connected by a common wire to the package pin corresponding to the chip pins connected to the via.

[0001] This application claims priority to prior Japanese applicationsJP 2003-53260 and 2004-50264, the disclosure of which is incorporatedherein by reference.

BACKGROUND OF THE INVENTION

[0002] This invention relates to a stacked semiconductor package and, inparticular, to a stacked DRAM package allowing high-speed data transfer.

[0003] Referring to FIG. 1, a conventional stacked semiconductor packagecomprises stackable semiconductor packages. Each of the stackablesemiconductor package comprises a substrate 102 provided with a cavity101 formed on a center portion of a top surface thereof, a wiringpattern 103 extending from the top surface to a bottom surface of thesubstrate 102, a semiconductor chip 104 disposed in the cavity 101 ofthe substrate 102, a plurality of bonding wires 105 connecting thesemiconductor chip 104 to the wiring pattern 103, and a plurality ofterminal pads 106 formed on the top surface of the substrate 102 andconnected to the wiring pattern 103, and a plurality of solder balls 107formed on the bottom surface of the substrate 102 to be connected andfixed to the wiring pattern 103.

[0004] The terminal pads 106 are arranged in a pattern identical to thatof the solder balls 107. In other words, the terminal pads 106 and thesolder balls 107 are arranged so that, if a plurality of such stackablesemiconductor packages are prepared and stacked on one another, thesolder balls 107 of an upper package are faced in one-to-onecorrespondence to the terminal pads 106 of a lower package adjacentthereto. Therefore, by stacking a plurality of stackable semiconductorpackages and carrying out a reflowing process, it is possible to obtainthe stacked package in which a plurality of semiconductor chips arestacked and connected to one another (for example, see Japanese PatentApplication Publication (JP-A) No. H11-220088).

[0005] Referring to FIG. 2, another conventional stacked semiconductorpackage comprises semiconductor chips 111 and flexible substrates 112wrapping the semiconductor chips 111 separately.

[0006] Referring to FIG. 3, each of the semiconductor chips 111 of thestacked semiconductor package illustrated in FIG. 2 has a bottom surfaceprovided with a plurality of contacts 121. On the other hand, each ofthe flexible substrate 112 has a top surface provided with a firstconductive pad array 122 arranged in a pattern (reversed pattern)corresponding to that of the contacts 121. The flexible substrate 112has a bottom surface provided with a second conductive pad arrayoverlapping and aligned with the first conductive pad array 122 in avertical direction (i.e., arranged in a pattern identical to that of thecontacts 121), and third and fourth conductive pad arrays formed onopposite sides of the second conductive pad array. Each of the third andthe fourth conductive pad arrays is arranged in a reversed pattern withrespect to a corresponding half of the second conductive pad array andis connected to the corresponding half of the second conductive padarray through a wiring pattern.

[0007] When the semiconductor chip 111 is mounted on the top surface ofthe flexible substrate 112, the contacts 121 of the semiconductor chip111 are connected to first conductive pads of the first conductive padarray 122 on the top surface of the flexible substrate 112 and, throughthe flexible substrate 112, are also connected to second conductive padsof the second conductive pad array located on the bottom surface of theflexible substrate 112. As a consequence, each of the contacts 121 ofthe semiconductor chip 111 is connected to a corresponding one of thepads contained in the third or the fourth conductive pad array. When theflexible substrate 112 is folded so as to wrap the semiconductor chip111, the third and the fourth conductive pad arrays are positioned abovea top surface of the semiconductor chip. That is, the third and thefourth conductive pad arrays face up. A fifth conductive pad arraydefined by the third and the fourth conductive pad arrays is arranged ina pattern identical to that of the first conductive pad array. Thus, thesemiconductor chip 111 and the corresponding flexible substrate 112 forma stackable semiconductor package.

[0008] By stacking a plurality of stackable semiconductor packageshaving the above-mentioned structure and heating the packages stacked onone another, the second conductive pad array of an upper package and thefifth conductive pad array of a lower package adjacent thereto areconnected by soldering to each other. As a result, the stacked packagecomprising the semiconductor packages stacked on one another andconnected to one another is obtained as illustrated in FIG. 2 (forexample, see U.S. Pat. No. 6,473,308).

[0009] Each of the conventional stacked semiconductor packages describedabove comprises stackable semiconductor packages each of which comprisesthe single substrate and the single semiconductor chip mounted thereto.That is, by stacking the stackable semiconductor packages, the stackedsemiconductor package is obtained. In the stacked package, pins (solderballs or conductive pads) of the lowermost stackable semiconductorpackage are used as external connection terminals (stacked package pins)while pins of each of the remaining stackable semiconductor packages areused for connection to a lower adjacent one of the stackablesemiconductor packages. Therefore, a wiring distance between the pins ofeach of the stackable semiconductor packages forming the stacked packageand the external connection terminals depends upon a stacked position ofeach stackable semiconductor package in a vertical direction.Specifically, an upper package has a longer wiring distance and a lowerpackage has a shorter wiring distance. Thus, the conventional stackedsemiconductor packages are disadvantageous in that the distance to theexternal connection terminals is different depending upon the stackedposition of each stackable semiconductor package.

SUMMARY OF THE INVENTION

[0010] It is an object of this invention to provide a stackedsemiconductor package which comprises a single substrate and twosemiconductor chips mounted thereto and which enables wiring lengthsfrom an external connection terminal to the semiconductor chips to besubstantially equal to each other.

[0011] It is another object of this invention to provide a stackedsemiconductor package which allows high-speed data transfer.

[0012] According to this invention, there is provided a stackedsemiconductor package comprising a substrate having first and secondsurfaces opposite to each other, and first and second semiconductorchips each of which has a mounting surface provided with a plurality ofchip pins arranged in a predetermined pattern, the first and the secondsemiconductor chips being mounted on the first and the second surfacesof the substrate, respectively, so that the mounting surfaces are facedto each other with the substrate interposed therebetween.

[0013] In the above-mentioned stacked semiconductor package, thesubstrate has a plurality of package pins corresponding to the chippins, respectively, and formed on the first or the second surface in anarea different from a chip mounting area where the first or the secondsemiconductor chip is mounted.

[0014] The package pins may be arranged in a pattern identical to thepredetermined pattern.

[0015] The package pins include an option pin connected to acorresponding chip pin of either one of the first and the secondsemiconductor chips and a regular pin connected to a corresponding chippin of each of the first and the second semiconductor chips.

[0016] The substrate has a common wire having one end connected to theregular pin, and a branch wire portion connecting the other end of thecommon wire to two chip pins as the corresponding chip pins of the firstand the second semiconductor chips, The wiring length from the one endof the common wire to either one of the corresponding chip pins issubstantially equal to that from the one end of the common wire to theother of the corresponding chip pins.

[0017] In order to make the wiring length from the one end of the commonwire to either one of the corresponding chip pins be substantially equalto that from the one end of the common wire to the other of thecorresponding chip pins, the branch wire portion comprises a via formedin the vicinity of an intermediate position between the two chip pinsand connected to the other end of the common wire, and first and secondbranch wires which are substantially equal to each other in length andwhich connect the via to the two chip pins.

[0018] In case where the two chip pins corresponding to the regular pinare faced to each other through the substrate, the branch wire portionhas a via directly connecting the two chip pins.

[0019] The substrate is a multilayer substrate having a ground planeand/or a power supply plane. The common wire and the branch wire portioneach forming a transmission line together with the ground plane and/orthe power supply plane.

[0020] The semiconductor chip may be an elemental chip (bare die), suchas a DRAM, produced by a wafer process (pre-process) or may have apackaged structure comprising a substrate and the elemental chip mountedon the substrate and electrically connected to the substrate.

BRIEF DESCRIPTION OF THE DRAWING

[0021]FIG. 1 is a sectional view of a conventional stacked semiconductorpackage;

[0022]FIG. 2 is a perspective view of another conventional stackedsemiconductor package;

[0023]FIG. 3 is an exploded perspective view for describing asemiconductor chip and a flexible substrate used in the stackedsemiconductor package illustrated in FIG. 2;

[0024]FIGS. 4A and 4B are a perspective view and a front view of astacked semiconductor package according to one embodiment of thisinvention, respectively;

[0025]FIG. 5 is a sectional view of a semiconductor chip having aconventional package structure;

[0026]FIG. 6 is a sectional view of a semiconductor chip having anotherconventional package structure;

[0027]FIG. 7 is a sectional view of a semiconductor chip having stillanother conventional package structure;

[0028]FIG. 8 is a perspective view of a semiconductor chip used in thestacked semiconductor package illustrated in FIGS. 4A and 4B;

[0029]FIG. 9 is a view showing an arrangement of pins of thesemiconductor chip illustrated in FIG. 8;

[0030]FIG. 10 is a view showing an arrangement of package pins of thestackable semiconductor package illustrated in FIGS. 4A and 4B;

[0031]FIG. 11 is a perspective view of a flexible substrate used in thestackable semiconductor package illustrated in FIGS. 4A and 4B;

[0032]FIGS. 12A and 12B are a perspective view and a vertical sectionalview showing the state before the semiconductor chips are mounted on theflexible substrate, respectively;

[0033]FIG. 13 is a sectional view for describing connection related tooption pins on the flexible substrate of FIG. 11;

[0034]FIG. 14 is a sectional view for describing connection related to aVDD plane in the flexible substrate of FIG. 11;

[0035]FIG. 15 is a sectional view for describing connection relatednormal regular pins on the flexible substrate of FIG. 11;

[0036]FIG. 16 is a sectional view for describing connection between padsdirectly connected to each other by a via in the flexible substrate ofFIG. 11;

[0037]FIGS. 17A and 17B show, as a part of wiring of the flexiblesubstrate, connection between a first chip connection pad array and anexternal connection pad array and connection between a second chipconnection pad array and vias connected to the external connection padarray, respectively;

[0038]FIGS. 18A and 18B are a perspective view and a vertical sectionalview for describing a transmission line formed as a microstrip line,respectively;

[0039]FIGS. 19A and 19B are a perspective view and a vertical sectionalview for describing another transmission line formed as a strip line,respectively;

[0040]FIGS. 20A and 20B are a perspective view and a vertical sectionalview for describing still another transmission line formed as a parallelline, respectively;

[0041]FIG. 21A is a perspective view showing a ground plate or a powersupplying plate comprising a plurality of ground/power supplying plateportions;

[0042]FIG. 21B is a perspective view showing another ground plate ofanother power supplying plate which is partly divided by a via and/oranother wire.

[0043]FIG. 22 is a schematic sectional view of a modification of thestacked semiconductor package according to this invention; and

[0044]FIGS. 23A and 23B are a schematic sectional view and a perspectiveview of another modification of the stacked semiconductor packageaccording to this invention, respectively.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0045] Now, a preferred embodiment of this invention will be describedin detail with reference to the drawings.

[0046] Referring to FIGS. 4A and 4B, a stacked semiconductor package 10according to one embodiment of this invention comprises a firstsemiconductor chip 11, a second semiconductor chip 12, and a flexiblesubstrate 13 on which the first and the second semiconductor chips 11and 12 are mounted. The flexible substrate 13 has top and bottomsurfaces as first and second surfaces opposite to each other.

[0047] The first semiconductor chip 11 is mounted on the top surface ofthe flexible substrate 13 in a chip mounting area (51 in FIG. 11) as oneof two areas defined by dividing the top surface into two halves. Thesecond semiconductor chip 12 is mounted on the bottom surface of theflexible substrate 13 to face the first semiconductor chip 11 with theflexible substrate 13 interposed therebetween. The first and the secondsemiconductor chips 11 and 12 are mounted to the flexible substrate 13,for example, by the use of solder balls.

[0048] The flexible substrate 13 is folded into two so as to wrap thesecond semiconductor chip 12. As a result of folding, the remaining area(52 in FIG. 11) of the top surface of the flexible substrate 13 becomesa bottom surface of the stacked semiconductor package 10 as a whole. Inthe remaining area, a plurality of package pins (solder balls) 14 areformed to serve as external connection terminals of the stackedsemiconductor package 10.

[0049] Next referring to FIGS. 5 through 11, each of the first and thesecond semiconductor chips 11 and 12 and the flexible substrate 13 willbe described in detail.

[0050] The first and the second semiconductor chips 11 and 12 aresimilar in structure to each other. Each of the first and the secondsemiconductor chips 11 and 12 may be a memory chip such as a DRAM.Furthermore, each of the first and the second semiconductor chips 11 and12 may be an elemental chip (or a bare die) formed by a wafer process(pre-process) or may have a packaged structure comprising a substrateand the above-mentioned elemental chip mounted on the substrate by apackaging process (post-process).

[0051] A semiconductor chip with the packaged structure, for example, isdisclosed in Japanese Patent Application Publication (JP-A) No.H11-135562 and is also disclosed in Japanese Patent ApplicationPublication (JP-A) No. H11-186449. The semiconductor chip has structureas illustrated in FIG. 5 or 6. In FIG. 5 or 6, the semiconductor chip ismanufactured by mounting an elemental chip 202 or 302 on a substrate 202or 301, electrically connecting wires (pads) 203 or 303 of the elementalchip 202 or 302 to wires on the substrate by means of wire bonding (orinner lead bonding, flip-chip connection, and so on), and encupsulatingthe elemental chip 202 or 302 and the substrate in a resin mold toprotect a conductive pattern on the substrate.

[0052] Alternatively, there is a semiconductor chip with anotherpackaged structure obtained according to a method in which a packagingprocess (post-process) is integrated with the wafer process(pre-process) and the packaging process is completed at a wafer level.The semiconductor chip is referred to as a wafer level CSP (Chip SizePackage or Chip Scale Package) or a wafer process package. For example,the semiconductor chip of the type is disclosed in Japanese PatentApplication Publication (JP-A) No. 2002-261192 and is also disclosed inJapanese Patent Application Publication (JP-A) No. 2003-298005. Asillustrated in FIG. 7, the semiconductor chip disclosed in the formerdocument is structured by forming a protection film 402, a rewiringlayer 403, a copper post 404 and the like on a semiconductor substratewhich undergo a wafer process, and encapsulating them in a resin mold405.

[0053] As illustrated in FIG. 8, each of the semiconductor chips 11 and12 has one surface (mounting surface) provided with a plurality of pins(semiconductor balls, may be called chip pins) 21 arranged in apredetermined pattern and adapted to be electrically and mechanicallyconnected to the flexible substrate 13.

[0054] Each of the chip pins 21 is assigned with a specific role(signal). For example, in case of a SDRAM for DDR-11, the chip pins 21are arranged in a matrix pattern and assigned with various roles asillustrated in FIG. 9. In FIG. 9, arrangement of the chip pins 21 isseen from an upper side. For example, in FIG. 9, a pin in row A andcolumn 1 (Al pin) is used for VDD.

[0055] Herein, description will be made of an arrangement of the packagepins 14 of the stacked semiconductor package 10. The package pins 14 arearranged in a pattern substantially identical to the predeterminedpattern of the chip pins 21 of the semiconductor chip 11 (or 12). Forexample, the package pins of the stacked semiconductor packagecomprising the SDRAMs stacked on each other are arranged in a patternshown in FIG. 10. In FIG. 10, those pins different from the pins in FIG.9 are depicted by bold letters.

[0056] Referring to FIGS. 9 and 10, the pins are generally classifiedinto data (DQ) pins and command/address (C/A) pins substantiallyarranged in an upper half portion and a lower half portion,respectively. In FIG. 10, six pins in three pairs depicted by the boldletters include chip selection pins (CS0 and CS1), clock pins (CKE0 andCKE1), and on-die termination pins (ODT0 and ODT1). These pins serve tooperate the first and the second semiconductor chips 11 and 12independently from each other. Each of these pins is connected to onlyone of the semiconductor chips. For example, if CS, CKE, and ODT of thefirst semiconductor chip 11 are connected to CO0, CKE0, and ODT0 of thepackage pins, respectively, CS, CKE, and ODT of the second semiconductorchip 12 are connected to CS1, CKE1, and ODT1, respectively.

[0057] Those package pins for operating the first and the secondsemiconductor chips 11 and 12 independently from each other are calledoption pins and the remaining package pins will be called regular pins.

[0058] The pin arrangement of the package pins of the stackedsemiconductor package illustrated in FIG. 10 includes the option pinsfor the second (or additional) semiconductor chip in addition to the pinarrangement of the chip pins for each single semiconductor chipillustrated in FIG. 9.

[0059] On the other hand, the flexible substrate 13 is a multilayerwiring substrate which is, for example, a four-layer substratecomprising four conductive layers, namely, upper and lower (orfront-side and rear-side) signal layers as two surface side layers andVDD and GND planes as two inner layers. Hereinafter, it is assumed thatthe flexible substrate 13 is the four-layer substrate.

[0060] As shown in FIG. 11, the chip mounting area 51 on the top surfaceof the flexible substrate 13 is provided with a plurality of chipconnection pads (first connection pad array) arranged in a patternidentical to the predetermined pattern of the pins 21 of the firstsemiconductor chip 11 so as to correspond to the pins 21 of the firstsemiconductor chip 11. In the remaining area 52 of the top surface ofthe flexible substrate 13, an external connection pad array including aplurality of external connection pads corresponding to the package pins(package pin array) 14 as the external connection terminals of thestacked semiconductor package 10 are formed in a mirror-image patternwith respect to the pin arrangement of the first semiconductor chip 11.On the bottom surface of the flexible substrate 13 and in an area 53 ona rear side of the chip mounting area 51, a plurality of chip connectionpads (second connection pad array) (not shown) are arranged in amirror-image pattern so as to correspond to the pins 21 of the secondsemiconductor chip 12. On the bottom surface of the flexible substrate13 and in an area 54 corresponding to the external connection pad array,a plurality of vias (506 of FIG. 13) connected to the externalconnection pads are formed. The flexible substrate 13 further has aplurality of wires (wiring patterns for signal lines) and other vias(603,604,608,610,612 of FIG. 14, 702 of FIG. 15, 803 of FIG. 16) toconnect the connection pads of the first and the second connection padarrays to the external connection pads (package pins) correspondingthereto, respectively. The wires are formed in the front and the rearsignal layers.

[0061] Referring to FIGS. 12A and 12B, the first and the secondsemiconductor chips 11 and 12 are mounted on the top and the bottomsurfaces of the flexible substrate 13 in the chip mounting areas,respectively. At this time, the first and the second semiconductor chips11 and 12 are reversed in position from each other as readily understoodfrom FIG. 12A. In this state, the A1 pin of the first semiconductor chip11 is positioned on a left side (left and back) while the A1 pin of thesecond semiconductor chip 12 is positioned on a right side (right andback).

[0062] Each pin of the first semiconductor chip 11 and the correspondingpin (having the same role) of the second semiconductor chip 12 in areversed relationship to each other are connected through each of thewires of the flexible substrate 13 to a corresponding one of the packagepins 14. However, in case of a pair of chip pins for independentlyoperating the first and the second semiconductor chips 11 and 12, onlyone of the chip pins in pair is connected to a corresponding one of thepackage pins 14.

[0063] After the first and the second semiconductor chips 11 and 12 aremounted on the flexible substrate 13, the flexible substrate 13 isfolded (folded into two) to wrap the second semiconductor chip 12. Then,the stacked semiconductor package 10 illustrated in FIGS. 4A and 4B isobtained. At this time, the package pins 14 are arranged in a samedirection and in an identical pattern with respect to the pins 21 of thefirst semiconductor chip 11. Therefore, the stacked semiconductorpackage 10 can be directly mounted on a board adapted to mount the firstsemiconductor chip 11 as an elemental chip (as far as the board isadapted to accommodate the option pins). This means that the boardhaving a mounting area required to mount the first semiconductor chip 11is able to mount a memory package having a twice storage capacity.

[0064] Hereinafter, description will be made of connection between theconnection pads connected to the first and the second semiconductorchips and the external connection pads.

[0065] The pins 21 of the first and the second semiconductor chips 11and 12 include the chip pins connected to the option pins of the packagepins 14 and the chip pins connected to the regular pins. The chip pinsconnected to the regular pins include those connected to the regularpins through the VDD plane or the GND plane and those connected to theregular pins through the front-side signal layer and/or the rear-sidesignal layer. The chip pins connected to the regular pins through thesignal layer(s) include those pins which are connected in the mannersuch that each pair of pins faced to each other are directly connectedthrough the one of the vias formed in the substrate. In order to realizethe above-mentioned connection between the chips, the pads are connectedin the following manner.

[0066] As shown in FIG. 13, in the first connection pad array, each pad501 for the chip pin connected to the option pin is connected throughthe wire (signal line) 502 included in the front-side signal layer ofthe flexible substrate 13 to the external connection pad 503 for thecorresponding option pin. On the other hand, in the second connectionpad array, each pad 504 for the chip pin connected to the option pin isconnected through the wire (signal line) 505 included in the rear-sidesignal layer of the flexible substrate 13 to the via 506 of the area 54of the bottom surface of the flexible substrate 13. The via 506 isconnected to the external connection pad 507 connected to thecorresponding option pin. Herein, each wire included in the rear-sidesignal layer is connected through the via of the area 54 to thecorresponding external connection pad.

[0067] As illustrated in FIG. 14, in the first connection pad array, thepads (VDD, VDDQ) 602 (only one shown) for the chip pins connectedthrough the VDD plane 601 to the regular pins are connected to the VDDplane 601 through the vias 603 formed therefrom towards the bottomsurface of the substrate 13. The VDD plane 601 is connected through thevias 604 to the corresponding external connection pads 605. Similarly,in the first connection pad array, the pads 607 (only one shown) for thechip pins connected through the GND plane 606 to the regular pins areconnected to the GND plane 606 through the vias 608 formed therefromtowards the bottom surface of the substrate 13. On the other hand, inthe second connection pad array, the pads 609 (only one shown) for thechip pins connected through the VDD plane 601 to the regular pins areconnected to the VDD plane 601 through the vias 610 formed therefromtowards the top surface of the substrate 13. Similarly, in the secondconnection pad array, the pads (VSS, VSSQ) 611 (only one shown) for thechip pins connected through the GND plane 606 to the regular pins areconnected to the GND plane 606 through the vias 612 formed therefromtowards the top surface of the substrate 13.

[0068] Herein, the pads (VDD, VDDQ) related to a power supply areconnected to the single VDD plane. Alternatively, VDD and VDDQ may beseparately wired by dividing the VDD plane in the same layer.Alternatively, VDD and VDDQ may be wired in empty space of thefront-side signal layer and/or the rear-side signal layer. Furthermore,an additional plane may be formed for either of the pads for VDD andVDDQ. The pads (VSS, VSSQ) connected to the GND plane may be wired inthe similar manner.

[0069] As illustrated in FIG. 15, in the first connection pad array,each pad 701 for the chip pin connected to the (normal) regular pinthrough the front-side signal layer and/or the rear-side signal layer(except those pads directly connected to the pads on the bottom surfacethrough the vias, which will later be described) is connected throughthe wire (branch wire) 703 included in the front-side signal layer tothe via 702 formed in the vicinity of an intermediate point of thecorresponding pads of the first and the second signal pads. Thecorresponding pad 704 of the second connection pad array is connected tothe same via 702 through the wire (branch wire) 705 included in therear-side signal layer. Thus, a pair of the pads 701,704 for a pair ofthe chip pins connected to each (normal) regular pin through the wiresof the signal layers are connected to each other through the via 702formed in the vicinity of the intermediate point therebetween. The via702 connected to the pair of the connection pads 701,704 is connected tothe external connection pad for the corresponding regular pin throughthe wire (common wire) 706 or 707 of the front-side or the rear-sidesignal layer. The branch wires 703 and 705 and the via 702 connectedtherebetween are referred to as a branch wire portion all together. Withthe above-mentioned structure, the lengths of the branch wires connectedto the pair of connection pads (chip pins) corresponding to each otherare substantially equal to each other (to the extent that no problem iscaused in practical use).

[0070] As shown in FIG. 16, in the first connection pad array, eachremaining connection pad 801 connected to the regular pins through thefront-side signal layer and/or the rear-side signal layer is connectedthrough the via 803 to the connection pad 802 of the second connectionpad array which is positioned on the rear side. This is because some ofthe pins of each semiconductor chip 11,12 may be exchanged in theirroles without causing any problem. For example, in case where the pinsof each semiconductor chip 11,12 are assigned with the roles asillustrated in FIG. 9, DQ0, DQ1, DQ2, and DQ3 pins of one of the firstand the second semiconductor chips 11,12 are faced to DQ1, DQ0, DQ3, andDQ2 pins of the other semiconductor chip. Herein, DQ0, D01, D02, and DQ3pins of each of the semiconductor chips may be exchanged in their rolesso that a pair of those pins faced to each other may be connected to thesame regular pin without causing any problem. Each of the connectionpads (801) of the first connection pad array connected to those pins isdirectly connected through the via 803 to each of the connection pads(802) of the second connection pad array which is located on the bottomside of the rear side. One of the pair of the connection pads 801, 802connected to each other through the via 803 is connected to thecorresponding regular pin through the wire 804 or 805 of the front-sideor the rear-side signal layer. In this case, the via 803 forms a branchwire portion while the wire 804 or 805 is a common wire connected to thebranch wire portion.

[0071] The corresponding connection pads which can be connected directlythrough the via may be connected to each other in a different manner,taking into account the convenience in design or production.Specifically, two connection pads corresponding to each other may beconnected by a via formed in the vicinity of an intermediate pointtherebetween in the manner similar to that mentioned above.Alternatively, the pins located on the front and the rear sides are notdirectly connected but are connected through a via formed at a separateposition by the use of wires. In case where the pads are directlyconnected through the via, the via is formed on the pads to directlyconnect the pads. Alternatively, the via may be formed in the vicinityof the pads to directly connect the pads as will readily be understood.

[0072] Next, description will be made of connection between the firstand the second connection pad arrays and the external connection pads,in particular, connection related to the connection pads for the chippins connected to the regular pins.

[0073] Referring to FIG. 17A, a part of the front-side signal layer ofthe flexible substrate 13 is shown (corresponding to the lines A to D ofthe semiconductor chip in FIG. 9). A part of the rear-side signal layerof the flexible substrate 13 corresponding to FIG. 17A is shown in FIG.17B. In both of FIGS. 17A and 17B, the flexible substrate 13 is seenfrom the top surface.

[0074] Referring to FIG. 17A, the connection pad for the A8 pin of thefirst semiconductor chip is connected through a front-side wire (branchwire) 71 to a via 72. On the other hand, as illustrated in FIG. 17B, theconnection pad for the A8 pin of the second semiconductor chip isconnected through a rear-side wire (branch wire) 73 to the via 72.Herein, the via 72 is formed in the vicinity of an intermediate pointbetween the connection pad for the A8 pin of the first semiconductorchip and the connection pad for the AS pin of the second semiconductorchip so that the lengths of the wires 71 and 73 are equal to each other.The wires 71 and 73 are formed so as to be substantially equal in lengthto each other and to serve as transmission lines (to be matched inimpedance). The via 72 is further connected through a wire (common wire)74 of the rear-side signal layer to a via 75 formed on the area 54 ofthe bottom surface and connected to the pad for the A8 package pin.

[0075] Like the connection pads for the AS pins, the connection pads forthe B3 pins of the first and the second semiconductor chips areconnected to each other through a via 76 formed in the vicinity of anintermediate point therebetween. Unlike the via 72 for the A8 pins, thevia 76 is connected through a signal line 77 of the front-side signallayer to the pad for the B3 package pin.

[0076] Like the connection pads for the A8 pins, the connection padscorresponding to the B7 pins of the first and the second semiconductorchips are connected to a via 78 on the rear side of the pad for the B7package pin.

[0077] As shown in FIG. 17A, the connection pads for the C2 pin and theD3 pin of the first semiconductor chip are connected through the wiresof the front-side signal layer to the external connection pads for theC8 package pin and the D7 package pin, respectively. Although notillustrated in the figure, these connection pads for the C2 and the D3pins are directly connected through the vias to the connection pads forthe C8 pin and the D7 pin of the second semiconductor chip on the rearside, respectively.

[0078] On the other hand, as shown in FIG. 17B, the connection pads forthe C2 pin and the D3 pin of the second semiconductor chip are connectedthrough the wires of the rear-side signal layer to the vias connected tothe C2 package pin and the D3 package pin, respectively. Although notillustrated in the figure, these connection pads for the C2 and the D3pins are connected through the vias to the connection pads for the C8pin and the D7 pin of the first semiconductor chip on the front side,respectively.

[0079] The pads connected to the VDD plate, such as the connection padsfor the Al pins, are directly connected by the vias to the VDD plane.This also applies to the pads connected to the GND plane.

[0080] The connection pads for the chip pins connected to the optionpins are connected through the wires of the front-side or the rear-sidesignal layer, in the manner similar to the connection pad for the C2 pinor the D3 pin of the first or the second semiconductor chip.

[0081] Next, the wires formed on the flexible substrate will bedescribed. The flexible substrate 13 is a multiplayer substrate having aground wire and/or a power supply wire. Most (preferably all) of signalwiring patterns form transmission lines together with the ground planeand/or the power supply plane (or wire). Referring to FIGS. 18 to 21,various structures of the transmission line formed by each signal wiringpattern will be described.

[0082] As illustrated in FIGS. 18A and 18B, the transmission line may bea microstrip line comprising a signal wiring pattern 81 and a groundplane and/or a power supply plane (flat wiring) 82 adjacent to thesignal wiring pattern 81. Alternatively, as illustrated in FIGS. 19A and19B, the transmission line may be a strip line comprising a signalwiring pattern 81 and a pair of ground plane and/or a power supply plane(flat wiring) 82 a and/or 82 b adjacent to the signal wiring pattern 81on opposite sides. As illustrated in FIGS. 20A and 20B, the transmissionline may be a parallel line comprising a signal wiring pattern 81 and aground wire and/or a power supply wire 83 flush with the signal wiringpattern 81 and extending parallel to the signal wiring pattern 81 on oneside (or opposite sides) thereof. The structure of the above-mentionedtransmission lines are properly selected and combined to form the signalwiring patterns.

[0083] The ground plane and/or the power supply plane (flat wiring) 82,82 a and 82 b forming the microstrip line or the strip line has a widthnot smaller than that of the signal wiring pattern.

[0084] Referring to FIG. 21A, the ground plane and/or the power supplyplane (flat wirng) forming the transmission line may comprise aplurality of ground plane parts and/or power supply wiring plane parts(plates).

[0085] Referring to FIG. 21B, the ground plane and/or the power supplyplane 82, 82 a, 82 b forming the transmission line may be partiallyseparated by a via 95 and/or another wire 96.

[0086] Although this invention has been described in conjunction withone embodiment thereof, this invention is not limited to the foregoingembodiment.

[0087] For example, in the foregoing description, the package pins arealigned with the chip pins of the first semiconductor chip in thevertical direction. Alternatively, as shown in FIG. 22, the package pinsmay be shifted in position in order to reduce the length of the commonwires. As shown in FIGS. 23A and 23B, the arrangement of the packagepins may be quite different from that of the chip pins of the firstsemiconductor chip.

What is claimed is:
 1. A stacked semiconductor package comprising asubstrate having first and second surfaces opposite to each other, andfirst and second semiconductor chips each of which has a mountingsurface provided with a plurality of chip pins arranged in apredetermined pattern, the first and the second semiconductor chipsbeing mounted on the first and the second surfaces of the substrate,respectively, so that the mounting surfaces are faced to each other withthe substrate interposed therebetween.
 2. A stacked semiconductorpackage according to claim 1, wherein the substrate has a plurality ofpackage pins corresponding to the chip pins, respectively, and formed onthe first or the second surface in an area different from a chipmounting area where the first or the second semiconductor chip ismounted.
 3. A stacked semiconductor package according to claim 2,wherein the package pins are arranged in a pattern identical to thepredetermined pattern.
 4. A stacked semiconductor package according toclaim 1, wherein the package pins include an option pin connected to acorresponding chip pin of either one of the first and the secondsemiconductor chips and a regular pin connected to a corresponding chippin of each of the first and the second semiconductor chips.
 5. Astacked semiconductor package according to claim 4, wherein: thesubstrate has a common wire having one end connected to the regular pinand a branch wire portion connecting the other end of the common wire totwo chip pins as the corresponding chip pins of the first and the secondsemiconductor chips; the wiring length from the one end of the commonwire to one of the corresponding chip pins being substantially equal tothat from the one end of the common wire to the other of thecorresponding chip pins.
 6. A stacked semiconductor package according toclaim 5, wherein: the branch wire portion comprises a via formed in thevicinity of an intermediate position between the two chip pins andconnected to the other end of the common wire, and first and secondbranch wires which are substantially equal to each other in length andwhich connect the via to the two chip pins.
 7. A stacked semiconductorpackage according to claim 5, wherein the two chip pins corresponding tothe regular pin are faced to each other through the substrate, thebranch wire portion has a via directly connecting the two chip pins. 8.A stacked semiconductor package according to claim 1, wherein thesubstrate is a multilayer substrate having a ground plane and/or a powersupply plane, the common wire and the branch wire portion each forming atransmission line together with the ground plane and/or the power supplyplane.
 9. A stacked semiconductor package according to claim 8, whereinthe transmission line comprises any one of a microstrip line, a stripline, and a parallel line.
 10. A stacked semiconductor package accordingto claim 9, wherein the ground plane and/or the power supply planeincludes a portion formed by a plurality of ground plane parts and/orpower supply plane parts or a portion partially separated by a via oranother wire.
 11. A stacked semiconductor package according to claim 1,wherein the semiconductor chip is an elemental chip (bare die), a chiphaving a packaged structure obtained by mounting the elemental chip on asubstrate, electrically connecting wires (pads) of the elemental chipand wires on the substrate by wire bonding, inner lead bonding,flip-chip connection, or the like, and encapsulating the chip and thesubstrate in a resin mold in order to protect a conductive pattern onthe substrate, or a wafer level CSP or wafer process package.